Inside Replay Essentials.txt

Inside_Replay_Essentials.txt is a rewritten version of the original documentation and is used during development of the CPX RR ROM only. The FlashMode e.g. is not described at all.

This document explains in short the register setup of the Retro Replay original
cartridge in non-flash mode. Since other ROM banking setups rather than the ones
we use as an "environment" for the RR code are possible the document may lack or
appear biased. Please comment!

The entry to the ROM is the bank 0 reset vector ($8000 -> CBM80) just like on AR
hardware. (TODO: Check Atomic and Nordic out of curiosity)
On RR hardware we _SHOULD_ initialise Bit 1, 2 and 6 of $DE01 to enable
the REU compatible memory mode, keep the freeze button working and disallow banking
of cart RAM other than from bank 0.

As a result any clone hardware emulating AR and RR hardware "seperately" in some
way should by default select to enable any accessory connector and of course the
REU compatible memory map. Clone devices such as the 1541u may choose to "ignore"
$de01 write accesses rendering it to a non-register effectively.
'''We hereby swear we will not use $de01 for setting reading back the current ROM bank!'''
(Note: $de01 is currently used for SilverSurfer detection but that needs fixing anyhow.)

Therefore $de01 can safely be ignored on hardware implementations of the register
setup as described below.

It should be possible to distinguish between real RR hardware and clones by simply
reading back our initialisation value from startup from RAM bank 0 of the cartridge.
This should reveal wether the $de01 register is available and was addressed or not.

There are side effects of course: Dropping the "AllowBank" bit on clone hardware
adds a little incompatibility but at least the RR team never found it to be a useful
feature.

RAM AllowBank usage would fragment RAM on banks 2 and above and in regards of using
it continously for e.g. storing source codes and alike it would be a bad idea to use.

So the ideal startup code looks like:
- hit $de01 and init RR
- read back $9e01 and check with previous write
- in any case continue - but be aware that 9e01 successful comparison means diff. HW


This leaves us with just one register at $de00 set to $00 on reset/powerup
which works like this on WRITE:

bit 7 - ROM bank selector (A15)
bit 6 - Restores memory map after freeze, GAME and EXROM "reset"
      - no function when not in freeze mode
bit 5 - 0 = ROM and 1 = RAM
bit 4 - ROM bank selector (A14)
bit 3 - ROM bank selector (A13)
bit 2 - 1 = cartridge kill
bit 1 - 1 = /EXROM high  (0 = "assert" and 1 = "de-assert")
bit 0 - 1 = /GAME  low   (1 = "assert" and 0 = "de-assert")


Reading $de00 should result in:
bit 7 - ROM bank selector (A15)
bit 6 - initialised with 1 by RR software (REU compat memory map)
      - clones should always return 1
bit 5 - 0 since no flash 
      - clones should always return 1
bit 4 - ROM bank selector (A14)
bit 3 - ROM bank selector (A13)
bit 2 - 1 when freeze button is pressed and 0 otherwise
bit 1 - initialised with 0 by RR software (AllowBank)
      - clones should always return 0
bit 0 - 0 = no flash


On freezing bank 0 is activated at $e000 so the NMI "vector" of bank 0 is leading
the freeze code further. Make sure to check out the return code which on current
RR needs to be aligned to a kernel RTS. :)

During freeze mode the RR hardware is keeping control over GAME and EXROM and
ignores any write accesses until bit 6 is set. On setting bit 6 of $de00 the
standard memory map will instantly be restored and GAME/EXROM can be used again.

Being in freeze mode allows ROM banks to be mapped by $de00 as before but of course
they are mapped to $e000. RAM can only be accessed on the free I/O1 area.